Low-inductance current paths for on-package power distributions and methods of assembling same

ABSTRACT

A micro-trace containing package substrate provides a low-inductance alternating-current decoupling path between a semiconductive device and a die-side capacitor.

FIELD

This disclosure relates to power delivery for semiconductor devicepackages.

BACKGROUND

Semiconductive device miniaturization connected to device packaging,includes challenges to allow high-speed and small volume interconnectsbetween dice, and delivering power to the dice for capacitor-assistedpower delivery.

BRIEF DESCRIPTION OF THE DRAWINGS

Disclosed embodiments are illustrated by way of example, and not by wayof limitation., in the figures of the accompanying drawings where likereference numerals may refer to similar elements, in which:

FIG. 1 is a cross-section elevation of a semiconductor package substratethat includes a micro-Copper trace according to an embodiment;

FIG. 2 is a cross-section elevation of a semiconductor package substratethat includes a micro-Copper trace according to an embodiment;

FIG. 3 is a cross-section elevation of at least a portion of asemiconductor device package according to an embodiment;

FIG. 4 is a cross-section elevation of a semiconductor package substratethat includes a micro-Copper trace according to an embodiment;

FIG. 5 is a cross-section elevation of a semiconductor package substratethat includes a micro-Copper trace according to an embodiment;

FIG. 6 is a cross-section elevation of at least a portion of asemiconductor device package according to an embodiment;

FIG. 7 is a cross-section elevation and partial projection of structuresfrom at least a portion of a multi-chip semiconductor package accordingto an embodiment;

FIG. 8 is a top plan of a semiconductor device package according to anembodiment;

FIG. 8A is a cross-section elevation of the semiconductor device packagedepicted in FIG. 8 according to an embodiment;

FIG. 9 is a process flow diagram according to several embodiments; and

FIG. 10 is included to show an example of a higher-level deviceapplication for the disclosed embodiments.

DETAILED DESCRIPTION

On-package alternating-current (AC) power delivery is provided in alow-inductance path, where access to die-side capacitors (DSCs) isprovided for capacitance-on-die (Cdie) sharing in multi-chip packages(MCPs), such that capacitance-on-die is improved and land-sidecapacitors are not primarily used. The low-inductance current paths alsopreserve useful ball array populations on the land side of asemiconductor package substrate.

In several embodiments, an additional thin metal layer, such asmicro-Copper (μCu) in the range from 2 to 10 micrometer (μm) is usedwith a dielectric layer that has a micro dielectric-layer thickness(μDL) in a range from 2 to 20 μm to facilitate low-inductance paths todie-side capacitors. Other trace thicknesses that are not the μCu trace,have a thickness in a range from 10 to 35 μm.

Disclosed are low-inductance AC paths that allow for DSCs and maximumdie-to-component distances. Consequently in-semiconductor packagesubstrate (“in-package”) AC paths are disclosed, under the die shadows,with useful capacitance-on-die distribution between regions of a givendie and die-side capacitors.

Disclosed embodiments include useful in-package paths including pathscloser to the land side than to the die side, and where useful, viceversa. Other disclosed embodiments include MCPs with the low-inductanceAC paths along μCu traces. Other disclosed embodiments includethermal-die MCPs with the low-inductance AC paths along μCu traces,where the thermal die occupies a keep-out zone (KOZ) equivalent space.In an embodiment, a μCu trace is made from a non-Copper material such assilver. Unless explicitly noted, the μCu trace embodiments areelectronics-grade copper. In any event, the μCu trace may be referred toas a micro trace when compared to via traces within the semiconductorpackage substrate

FIG. 1 is a cross-section elevation of a semiconductor package substrate100 that includes a micro-Copper trace according to an embodiment. In anembodiment, a micro-Copper (μCu) trace 110 is formed above a microdielectric layer (μDL) 112. A direct-current, power-supply (VCC DC) via114 contacts a VCC top trace 116 and a VCC bottom trace 118. Adirect-current voltage-source source (VSS DC) return path includes a VSSvia 120 that contacts a VSS top trace 122 and a VSS bottom trace 124. Inthe illustrated embodiment, the μCu trace 110 is an alternating-currentvoltage-source source (VSS AC) return trace 110 that contacts the VSS DCvia 120. The μCu trace 110 may also be referred to as a micro trace 110because it is thinner when comparing thickness (Z-direction) to the topand bottom traces.

In an embodiment, the micro dielectric layer 112 is formed by spinningon dielectric material over the VCC DC bottom trace 118 and the VSS DCbottom trace 124, curing the dielectric material, and backgrinding orpolishing to achieve a μDL thickness 113 above other structures. In anembodiment, the μDL 112 has a thickness that facilitates a usefulinductance path from a landside capacitor. After configuring the μDL 112with the useful μDL thickness 113, a thin VSS copper material is formedand patterned to a μCu trace thickness 111. In an embodiment, the μCulayer 110 has a thickness 111 in a range from 2-10 μm and the μDL 112has a thickness 113 in a range from 4-20 μm.

A subsequent dielectric layer 126 is formed over the patterned μCu trace110 and the μDL 112. In an embodiment, the subsequent dielectric layer126 has a thickness 129 such as in a range from 25 μm to 40 μm. Afterforming the subsequent dielectric layer 126, the respective VCC DC and.VSS DC vias 114 and 120 are formed by laser drilling into the subsequentdielectric layer 126 as well as the μCu trace 110 and the μDL, 112,stopping on the VCC DC bottom trace 118 and the VSS DC bottom trace 124,and filling such as by electroplating electronics grade copper. Wherepatterning of the μCu trace 110 creates voids, the VCC via 114 avoidsshorting into the μCu trace 110.

The microvias that span two copper layers for the top and bottom traces,serve to connect the VSS alternating-current path that is supplied inthe μCu layer 110. In an embodiment, location of the VSS layer 110 iscloser to the respective bottom traces 118 and 124 than to the toptraces 116 and 122.

FIG. 2 is a cross-section elevation of a semiconductor package substrate200 that includes a micro-Copper trace according to an embodiment. In anembodiment, a micro-Copper (μCu) trace 210 is formed above a microdielectric layer (μDL) 212. A direct-current, power-supply (VCC DC) via214 contacts a VCC top trace 216 and a VCC bottom trace 218. Adirect-current voltage-source source (VSS DC) return path includes a VSSvia 220 that contacts a VSS top trace 222 and a VSS bottom trace 224.

In an embodiment, the micro dielectric layer 212 is formed by spinningon dielectric material over the VCC DC bottom trace 218 and the VSS DCbottom trace 224, curing the dielectric material, and backgrinding orpolishing to achieve a μDL thickness 213 above other structures. The μDL212 has a thickness that facilitates useful inductance path to alandside capacitor.

In the illustrated embodiment, the μCu trace 210 is analternating-current voltage-supply (VCC AC) supply trace 210 thatcontacts the VCC DC via 214.

After configuring the μDL, 212 with the useful μDL, thickness 213, athin VCC copper material is formed and patterned to a μCu tracethickness 211.

A subsequent dielectric layer 226 is formed over the patterned μCu trace210 and the μDL 212. In an embodiment, the subsequent dielectric layer226 has a thickness 229 such as in a range from 25 μm to 40 μm. Afterforming the subsequent dielectric layer 226, the respective VCC DC andVSS vias 214 and 220 are formed by laser drilling into the subsequentdielectric layer 226 as well as the μCu trace 210 and the μDL 212,stopping on the VCC DC bottom trace 218 and the VSS DC bottom trace 224,and filling such as by electroplating electronics grade copper. Wherepatterning of the μCu trace 210 does not create voids, the VCC via 214contacts the VCC AC μCu trace 210.

The microvias that span two copper layers for the top and bottom traces,serve to connect the VCC alternating-current path that is carried in theμCu layer 210. In an embodiment, location of the VCC μC layer 210 iscloser to the bottom traces 218 and 224 than to the top traces 216 and222.

FIG. 3 is a cross-section elevation of at least a portion of asemiconductor device package 300 according to an embodiment.

In an embodiment, a micro-Copper (μCu) trace 310 is formed above a microdielectric layer (μDL) 312. A direct-current, power-supply (VCC DC) via314 contacts a VCC top trace 316 and a VCC bottom trace 318. Adirect-current voltage-source source (VSS DC) return path includes a VSSvia 320 that contacts a VSS top trace 322 and a VSS bottom trace 324. Inthe illustrated embodiment, the μCu trace 310 is an alternating-currentvoltage-source source (VSS AC) return trace 310 that contacts the VSS DCvia 320.

In an embodiment, the micro dielectric layer 312 is formed by spinningon dielectric material over the VCC DC bottom trace 318 and the VSS DCbottom trace 324, curing the dielectric material, and backgrinding orpolishing to achieve a μDL thickness 313 above other structures such asabove a package core (not illustrated). The μDL 312 has a thickness 313that facilitates a useful inductance path from a landside capacitor.After forming the μDL 312 with the useful μDL thickness 313, a thin VSScopper material is formed and patterned to a μCu trace thickness 311. Inan embodiment, the micro trace 310 is a silver (Ag) material.

A subsequent dielectric layer 326 is formed over the patterned μCu trace310 and the μDL 312 to form a subsequent dielectric layer thickness 329.Several IDLs are formed above the patterned μCu trace 310 (depictedgenerally in simplified form) and the μDL 312, until a die side 327 ofsemiconductor package substrate 328 supports a first semiconductivedevice 330, and a landside 325 of the semiconductor package substrate328 supports a ball-grid array, one electrical bump of which isreference with numeral 332.

In an embodiment, a die-side capacitor 334 is seated on the die side 327of the semiconductor package substrate 328, and a keep-out zone (KOZ)336, as well as a memory-die stack 338 necessitate a capacitor-to-diehorizontal distance 340. A KOZ is a space adjacent a flip-chip die edge,and optionally an adjacent component, where underfill material willflow, and where a portion of the underfill material will possiblyremain. In any event, the KOZ 336 creates more lateral distance between,e.g. a die-side capacitor 334 and, e.g. a semiconductive device 330 itis servicing.

In an embodiment, the memory-die stack 338 includes a first larger diethat is flip-chip mounted on the die side 327, and the first larger dieincludes a through-silicon via (TSV) 339 that begins communication to astacked memory die; in this illustrated embodiment with three stackedmemory dice. In an embodiment, the first larger die includes amemory-controller hub (MCH) in the semiconductive active area that isaccessed by the TSV 339.

The vertical (Z-direction) scale is exaggerated for illustrativeclarity, and the capacitor-to-die horizontal distance 340 amounts to amajority of the total decoupling path between the die-side capacitor 334and the semiconductive device 330.

In an embodiment, the location of the μCu trace 310 is closer to thebottom traces 318 and 324 than to the top traces 316 and 320.

In an embodiment, the semiconductor package substrate 328 is assembledto a land 342 such as a motherboard 342. In an embodiment, the land 342includes a shell 344 that provides at least one of physical andelectrical-insulation protection to the semiconductive device 330.

In an embodiment, analysis of power delivery is done using thearchitecture depicted in FIG. 3, where the capacitor-to-die horizontaldistance is 12.7 mm, a 2 μm thick μCu trace 310 and a 4 μm μDT 312 abovea core layer (not illustrated) is carried out using the detailarchitecture depicted in FIG. 1. Compared to using a trace the thicknessof the VSS DC bottom trace 124 of 15 μm Cu, loop inductance is loweredby about 60 picalenry (pH), AC impedance at the peak is reduced by about4.6 milli Ohm (mOhm), and a baseline standard power-delivery path thatrequired 23 die-side capacitors, with this analysis, uses eight die-sidecapacitors to match the AC impedance of the comparison package.

FIG. 4 is a cross-section elevation of a semiconductor package substrate400 that includes a micro-Copper trace according to an embodiment. In anembodiment, a micro-Copper (μCu) trace 410 is formed before and belowwhere a micro dielectric layer (μDL) 412 is to be formed. Adirect-current, power-supply (VCC DC) via 414 contacts a VCC top trace416 and a VCC bottom trace 418. A direct-current voltage-source source(VSS DC) return path includes a VSS via 420 that contacts a VSS toptrace 422 and a VSS bottom trace 424. In the illustrated embodiment, theμCu trace 410 is an alternating-current voltage-source source (VSS AC)return trace 410 that contacts the VSS DC via 420.

In an embodiment, the micro dielectric layer 412 is formed by spinningon dielectric material over the μCu trace 410, curing the dielectricmaterial, and backgrinding or polishing to achieve a μDL thickness 413above other structures. The μDL 412 has a thickness that facilitatesuseful inductance path from a die-side capacitor. After forming the μDL412 with the useful μDL thickness 413, a thin VSS copper material isformed and patterned to a μCu trace thickness 411. In and embodiment,the micro trace 410 is a silver (Ag) material.

A penultimate dielectric layer 426 is formed before and below where thepatterned μCu trace 410 and the μDL 412 will be assembled. In anembodiment, the penultimate dielectric layer 426 has a thickness 429such as in a range from 25 μm to 40 μm. After forming the μCu trace 410,the μDL 412 is configured the penultimate dielectric layer 426, therespective VCC DC and VSS DC vias 414 and 420 are formed by laserdrilling into the penultimate dielectric layer 426, as well as the μCutrace 410 and the μDL layer 412, stopping on the VCC DC bottom trace 418and the VSS DC bottom trace 424, and filling such as by electroplatingelectronics grade copper. Where patterning of the μCu trace 410 createsvoids, the VCC via 414 avoids shorting into the μCu trace 410.

The microvias that span two copper layers for the top and bottom traces,serve to connect the VSS alternating-current path that is supplied bythe μCu trace 410. In an embodiment, location of the VSS μCu trace 410is closer to the top traces 416 and 422 than to the bottom traces 418and 424.

FIG. 5 is a cross-section elevation of a semiconductor package substrate500 that includes a micro-Copper trace according to an embodiment. In anembodiment, a micro-Copper (μCu) trace 510 is formed before and belowwhere a micro dielectric layer (μDL) 512 is to be formed. Adirect-current, power-supply (VCC DC) via 514 contacts a VCC top trace516 and a VCC bottom trace 518. A direct-current voltage-source source(VSS DC) return path includes a VSS via 520 that contacts a VSS toptrace 522 and a VSS bottom trace 524.

In an embodiment, the micro dielectric layer 512 is formed by spinningon dielectric material over the μCu trace 510, curing the dielectricmaterial, and backgrinding or polishing to achieve a μDL thickness 513above other structures. The μDL 512 has a thickness that facilitatesuseful inductance path to a die-side capacitor.

In the illustrated embodiment, the μCu trace 510 is analternating-current voltage-supply (VCC AC) supply trace 510 thatcontacts the VCC DC via 514.

The μCu trace 510 is formed, followed by configuring the μDL 512 withthe useful μDL thickness 513.

A penultimate dielectric layer 526 is formed before and below thepatterned μCu trace 510 and the μDL 512 are formed. In an embodiment,the penultimate dielectric layer 526 has a thickness 527 such as in arange from 25 μm to 40 μm. After forming the penultimate dielectriclayer 526, the respective VCC DC and VSS DC vias 514 and 520 are formedby laser drilling into the penultimate dielectric layer 526 as well asthe μCu trace 510 and the μDL 512, stopping on the VCC DC bottom trace518 and the VSS DC bottom trace 524, and filling such as byelectroplating electronics grade copper. Where patterning of the μCutrace 510 does not create voids, the VCC via 514 contacts the VCC AC μCutrace 510.

The microvias that span two copper layers for the top and bottom traces,serve to connect the VCC alternating-current path that is provided bythe μCu trace 510. In an embodiment, location of the VCC μCu trace 510is closer to the top traces 516 and 522 than to the bottom traces 518and 524.

FIG. 6 is a cross-section elevation of at least a portion of asemiconductor device package 600 according to an embodiment.

In an embodiment, a micro-Copper (μCu) trace 610 is formed below a microdielectric layer (μDL) 612. A direct-current, power-supply (VCC DC) via614 contacts a VCC top trace 616 and a VCC bottom trace 618. Adirect-current voltage-source source (VSS DC) return path includes a VSSvia 620 that contacts a VSS top trace 622 and a VSS bottom trace 624. Inthe illustrated embodiment, the μCu trace 610 is an alternating-currentvoltage-source source (VSS AC) return trace 610 that contacts the VSS DCvia 620.

In an embodiment, the micro dielectric layer 612 is formed by spinningon dielectric material over the μCu trace 610, curing the dielectricmaterial, and backgrinding or polishing to achieve a μDL thickness 613above other structures. The μDL 612 has a thickness 613 that facilitatesa useful inductance path from a die-side capacitor. After forming theμDL 612 with the useful μDL thickness 313, a thin VSS copper material isformed and patterned to a μCu trace thickness 611. In an embodiment, themicro trace 610 is a silver (Ag) material.

A penultimate dielectric layer 626 is formed below and before thepatterned μCu trace 610 and the μDL 612 are to be formed, and thepenultimate dielectric layer 626 forms a penultimate dielectric layerthickness 629. Several IDLs are depicted generally and they are formedbelow the patterned μCu trace 610 and the μDL 612, and a die side 627 ofa semiconductor package substrate 628 supports a first semiconductivedevice 630, and a landside 625 of the semiconductor package substrate628 supports a ball-grid array, one electrical bump of which isreference with numeral 632.

In an embodiment, a die-side capacitor 634 is seated on the die side 627of the semiconductor package substrate 628, and a keep-out zone 636, aswell as a memory-die stack 638 necessitate a capacitor-to-die horizontaldistance 640. In an embodiment, the memory-die stack 638 includes afirst larger die that is flip-chip mounted on the die side 627, and thefirst larger die includes a through-silicon via (TSV) 639 that beginscommunication to a stacked memory die; in this illustrated embodimentwith three stacked memory dice. In an embodiment, the first larger dieincludes a memory-controller hub (MCH) in the semiconductive active areathat is accessed by the TSV 639.

The vertical (Z-direction) scale is exaggerated for illustrativeclarity, and the capacitor-to-die horizontal distance 640 amounts to amajority of the total decoupling path between the die-side capacitor 634and the semiconductive device 630. The location of the μCu trace 610 iscloser to the top traces 616 and 620 than to the bottom traces 618 and624 in a configuration as illustrated in FIG. 4.

In an embodiment, the semiconductor package substrate 628 is assembledto a land 642 such as a motherboard 642. In an embodiment, the land 642includes a shell 644 that provides at least one of physical andelectrical-insulation protection to at least the semiconductive device630.

FIG. 7 is a cross-section elevation and partial projection of structuresfrom at least a portion of a multi-chip semiconductor package (MCP) 700according to an embodiment. Multiple dice such as multiple processors730 and 731 are coupled to at least one die-side capacitor 734 accordingto an embodiment.

In an embodiment, a micro-Copper (μCu) trace 710 is formed above a microdielectric layer (μDL) 712. A direct-current, power-supply (VCC DC) via714 contacts a VCC top trace and a VCC bottom trace. A direct-currentvoltage-source source (VSS DC) return path includes a VSS via 720 thatcontacts a VSS top trace and a VSS bottom trace. In the illustratedembodiment, the μCu trace 710 is an alternating-current voltage-sourcesource (VSS AC) return trace 610 that contacts the VSS DC via 720.

In an embodiment, the micro dielectric layer 712 is formed by spinningon dielectric material above other structures, curing the dielectricmaterial, and backgrinding or polishing to achieve a μDL thickness. TheμCu trace 710 is formed and patterned on the μDL 712. The μDL 712 has athickness that facilitates a useful inductance path from a landsidecapacitor 734. After forming the μDL 712 with the useful μDL thickness,a thin VSS copper material 710 is formed and patterned to a μCu tracethickness. In an embodiment, the micro trace 710 is made from a silver(Ag) material.

A subsequent dielectric layer 726 is formed over the patterned μCu trace710 and the μDL 712 to form a subsequent dielectric layer thickness. Atleast one interlayer dielectric (ILD) is formed below the patterned μCutrace 710 and the μDL 712. In an embodiment, a die side 727 of asemiconductor package substrate 728 supports the first semiconductivedevice 730 and the subsequent semiconductive device 731, and a landside725 of the semiconductor package substrate 728 supports a ball-gridarray, one electrical bump of which is reference with numeral 732.

In an embodiment, a die-side capacitor 734 is seated on the die side 727of the semiconductor package substrate 728, and a KOZ 736 necessitatesdifferent capacitor-to-die horizontal distances for each of thesemiconductive devices 730 and 731. In an embodiment, the μCu trace 710is connected and configured as illustrated in FIG. 1. In an embodiment,the μCu trace 710 is connected and configured as illustrated in FIG. 2.In an embodiment, the μCu trace 710 is connected and configured asillustrated in FIG. 1. In an embodiment, the μCu trace 710 is connectedand configured as illustrated in FIG. 4. In an embodiment, the μCu trace710 is connected and configured as illustrated in FIG. 5.

In an embodiment, the location of the μCu trace 710 is closer to the toptraces than to the bottom traces. In an embodiment as illustrated, thelocation of the μCu trace 710 is closer to the bottom traces than to thetop traces.

FIG. 8 is a top plan of a semiconductor device package 800 according toan embodiment. In an embodiment, a multi-die complex used “dummy” diceto improve the multi-die arrangement, and to channel excess heat to aheat sink such as an integrated heat spreader. In an embodiment askeep-out zones are bridged as depicted in FIGS. 3 and 6,quick-voltage-droop issues are similarly addressed where the dummy diceessentially take up the space that otherwise would be the KOZs.Consequence, a low-conductance thermal path is enabled frommetal-insulator-metal layers on the dummy dice that need supplementalcapacitance-on-die. A low-inductance alternating-current path enables auseful connection to transfer the capacitance-on-die from the thermaldice to the main semiconductor device.

A first semiconductive device 830 is seated on a die side of asemiconductor package substrate 828, and several other semiconductivedevices are also grouped near the first semiconductive device 830. In anembodiment a subsequent semiconductive device 852 is seated opposite athird semiconductive device 854 and across from the first semiconductivedevice 830. Further in an embodiment, a fourth semiconductive device 856is seated opposite a fifth semiconductive device 858 and across from thefirst semiconductive device 830.

In an embodiment, heat management is facilitated by a first heat sink860 (also referred to as a first thermal die 860 or “dummy die” 860) anda subsequent heat sink 862 (also referred to as a subsequent thermal die862 or “dummy die” 862), across from the first semiconductive device830. In an embodiment, the first thermal die 860 includes ametal-insulator-metal structure 861 that provides decoupling capability.In an embodiment, the subsequent thermal die 862 includes ametal-insulator-metal structure 863 that provides decoupling capability,

By placing the first thermal die 860 and the subsequent thermal die 862near the first semiconductive device 830, and also near thesemiconductive devices 852, 854, 856 and 858, heat management isfacilitated, as well as low-inductance AC pathways are enabled betweendie-side capacitors and the main semiconductive device 830.

FIG. 8A is a cross-section elevation of the semiconductor device package800 depicted in FIG. 8 according to an embodiment. The cross-sectionview is taken from FIG. 8A along the section line 8A-8A. In anembodiment, a μCu trace 810 is coupled to the first semiconductivedevice 830 as well as to the first and subsequent thermal dice 860 and862. In an embodiment, the first thermal die 860 includes ametal-insulator-metal structure 861 that provides decoupling capability.In an embodiment, the subsequent thermal die 862 includes ametal-insulator-metal structure 863 that provides decoupling capability.

As illustrated in an embodiment, the μCu trace 810 is an AC tracesimilar in configuration any of the AC configurations depicted in any ofFIGS. 1, 2, 3, 4, 5 and 6.

FIG. 9 is a process flow diagram 900 according to several embodiments.

At 910, the process includes configuring a micro dielectric layer tocontact a micro-copper trace. In a non-limiting example embodiment, theμDL 112 is spun on, cured and thinned to the thickness 113, and a μCutrace 110 is formed above and on the μDL 112. In a non-limiting exampleembodiment, the μDL 412 is spun on, cured and thinned to the thickness113, below the μCu trace 310.

At 920, the process includes contacting the micro-copper trace to one ofa VSS DC via and VCC DC via in a semiconductor package substrate. In anonlimiting example embodiment, the VSS DC via 120 is formed by laserdrilling to expose the VSS bottom trace 124 and filling in the via 120to contact the VSS AC μCu trace 110. In a nonlimiting exampleembodiment, the VCC DC via 214 is formed by laser drilling to expose theVCC bottom trace 218 and filling in the via 214 to contact the VCC ACμCu trace 210.

At 930, the process includes coupling a die-side capacitor to the μCutrace. In a non-limiting example embodiment, the μCu trace 310 iscoupled to the die-side capacitor 334. In a non-limiting exampleembodiment, the μCu trace 610 is coupled to the die-side capacitor 634.

At 940, the process includes coupling the μCu trace to a semiconductivedevice. In a non-limiting example embodiment, the semiconductive device330 is coupled to the μCu trace 310, and consequently the semiconductivedevice 330 is coupled to the die-side capacitor 334 through the μCutrace 310.

At 950, the process includes assembling the semiconductive device to acomputing system.

FIG. 10 is included to show an example of a higher-level deviceapplication for the disclosed embodiments. The micro-trace containingpackage substrate embodiments may be found in several parts of acomputing system. In an embodiment, the micro-trace containing packagesubstrate embodiments can be part of a communications apparatus such asis affixed to a cellular communications tower. In an embodiment, acomputing system 1000 includes, but is not limited to, a desktopcomputer. In an embodiment, a system 1000 includes, but is not limitedto a laptop computer. In an embodiment, a system 1000 includes, but isnot limited to a tablet. In an embodiment, a system 1000 includes, butis not limited to a notebook computer. In an embodiment, a system 1000includes, but is not limited to a personal digital assistant (PDA). Inan embodiment, a system 1000 includes, but is not limited to a server.In an embodiment, a system 1000 includes, but is not limited to aworkstation. In an embodiment, a system 1000 includes, but is notlimited to a cellular telephone. In an embodiment, a system 1000includes, but is not limited to a mobile computing device. In anembodiment, a system 1000 includes, but is not limited to a smart phone.In an embodiment, a system 1000 includes, but is not limited to aninternet appliance. Other types of computing devices may be configuredwith the microelectronic device that includes micro-trace containingpackage substrate embodiments.

In an embodiment, the processor 1010 has one or more processing cores1012 and 1012N, where 1012N represents the Nth processor core insideprocessor 1010 where N is a positive integer. In an embodiment, theelectronic device system 1000 using a micro-trace containing packagesubstrate embodiment that includes multiple processors including 1010and 1005, where the processor 1005 has logic similar or identical to thelogic of the processor 1010. In an embodiment, the processing core 1012includes, but is not limited to, pre-fetch logic to fetch instructions,decode logic to decode the instructions, execution logic to executeinstructions and the like. In an embodiment, the processor 1010 has acache memory 1016 to cache at least one of instructions and data for themulti-layer solder resist on a semiconductor device package substrate inthe system 1000. The cache memory 1016 may be organized into ahierarchical structure including one or more levels of cache memory.

In an embodiment, the processor 1010 includes a memory controller 1014,which is operable to perform functions that enable the processor 1010 toaccess and communicate with memory 1030 that includes at least one of avolatile memory 1032 and a non-volatile memory 1034. In an embodiment,the processor 1010 is coupled with memory 1030 and chipset 1020. In anembodiment, the chipset 1020 is part of a micro-trace containing packagesubstrate embodiment depicted in FIG. 2. The processor 1010 may also becoupled to a wireless antenna. 1078 to communicate with any deviceconfigured to at least one of transmit and receive wireless signals. Inan embodiment, the wireless antenna interface 1078 operates inaccordance with, but is not limited to, the IEEE 802.11 standard and itsrelated family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth,WiMax, or any form of wireless communication protocol.

In an embodiment, the volatile memory 1032 includes, but is not limitedto, Synchronous Dynamic Random Access Memory (SDRAM), Dynamic RandomAccess Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM),and/or any other type of random access memory device. The non-volatilememory 1034 includes, but is not limited to, flash memory, phase changememory (PCM), read-only memory (ROM), electrically erasable programmableread-only memory (EEPROM), or any other type of non-volatile memorydevice.

The memory 1030 stores information and instructions to be executed bythe processor 1010. In an embodiment, the memory 1030 may also storetemporary variables or other intermediate information while theprocessor 1010 is executing instructions. In the illustrated embodiment,the chipset 1020 connects with processor 1010 via Point-to-Point (PtP orP-P) interfaces 1017 and 1022. Either of these PtP embodiments may beachieved using a micro-trace containing package substrate embodiment asset forth in this disclosure. The chipset 1020 enables the processor1010 to connect to other elements in a micro-trace containing packagesubstrate embodiment in a system 1000. In an embodiment, interfaces 1017and 1022 operate in accordance with a PtP communication protocol such asthe Intel® QuickPath Interconnect (QPI) or the like. In otherembodiments, a different interconnect may be used.

In an embodiment, the chipset 1020 is operable to communicate with theprocessor 1010, 1005N, the display device 1040, and other devices 1072,1076, 1074, 1060, 1062, 1064, 1066, 1077, etc. The chipset 1020 may alsobe coupled to a wireless antenna 1078 to communicate with any deviceconfigured to at least do one of transmit and receive wireless signals.

The chipset 1020 connects to the display device 1040 via the interface1026. The display 1040 may be, for example, a liquid crystal display(LCD), a plasma display, cathode ray tube (CRT) display, or any otherform of visual display device. In an embodiment, the processor 1010 andthe chipset 1020 are merged into a micro-trace containing packagesubstrate embodiment in a system. Additionally, the chipset 1020connects to one or more buses 1050 and 1055 that interconnect variouselements 1074, 1060, 1062, 1064, and 1066. Buses 1050 and 1055 may beinterconnected together via a bus bridge 1072 such as at least onemicro-trace containing package substrate embodiment. In an embodiment,the chipset 1020, via interface 1024, couples with a non-volatile memory1060, a mass storage device(s) 1062, a keyboard/mouse 1064, a networkinterface 1066, smart TV 1076, and the consumer electronics 1077, etc.

In an embodiment, the mass storage device 1062 includes, but is notlimited to, a solid-state drive, a hard disk drive, a universal serialbus flash memory drive, or any other form of computer data storagemedium. In one embodiment, the network interface 1066 is implemented byany type of well-known network interface standard including, but notlimited to, an Ethernet interface, a universal serial bus (USB)interface, a Peripheral Component Interconnect (PCI) Express interface,a wireless interface and/or any other suitable type of interface. In oneembodiment, the wireless interface operates in accordance with, but isnot limited to, the IEEE 802.11 standard and its related family, HomePlug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form ofwireless communication protocol.

While the modules shown in FIG. 10 are depicted as separate blockswithin the micro-trace containing package substrate embodiments in acomputing system 1000, the functions performed by some of these blocksmay be integrated within a single semiconductor circuit or may beimplemented using two or more separate integrated circuits. For example,although cache memory 1016 is depicted as a separate block withinprocessor 1010, cache memory 1016 (or selected aspects of 1016) can beincorporated into the processor core 1012.

To illustrate the micro-trace containing package substrate embodimentsand methods disclosed herein, a non-limiting list of examples isprovided herein:

Example 1 is a semiconductor package substrate comprising: a VCC viabetween a VCC top trace and a VCC bottom trace; a VSS via between a VSStop trace and a VSS bottom trace, wherein the VSS via is adjacent theVCC via; a micro trace that contacts only one of the VCC via and VSSvia, wherein the micro trace is between the VCC and VSS top traces andthe VCC and VSS bottom traces, and wherein the micro trace is thinnerthan any of the VSS and VCC top traces and the VSS and VCC bottomtraces; and a mica dielectric layer contacting the micro trace, whereinthe micro dielectric layer contacts one of the VCC and VSS top tracesand the VCC and VSS bottom traces.

In Example 2, the subject matter of Example 1 optionally includeswherein micro trace is closer to the VSS and VCC bottom traces than tothe VSS and VCC top traces.

In Example 3, the subject matter of any one or more of Examples 1-2optionally include wherein micro trace is closer to the VSS and VCC toptraces than to the VSS and VCC bottom traces.

In Example 4, the subject matter of any one or more of Examples 1-3optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to theland side than to the die side, further including a capacitor on the dieside.

In Example 5, the subject matter of any one or more of Examples 1-4optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to theland side than to the die side, further including: a capacitor on thedie side; and a semiconductive device on the die side, wherein the microtrace couples the capacitor to the semiconductive device.

In Example 6, the subject matter of any one or more of Examples 1-5optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to theland side than to the die side, further including: a capacitor on thedie side; a semiconductive device on the die side, wherein the microtrace couples the capacitor to the semiconductive device; and amemory-die on the die side, wherein the memory die is between thesemiconductive device and the capacitor, and wherein a keep-out zone isbetween the memory die and the capacitor.

In Example 7, the subject matter of any one or more of Examples 1-6optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to theland side than to the die side, further including: a capacitor on thedie side; and a semiconductive device on the die side, wherein the microtrace couples the capacitor to the semiconductive device, and whereinthe micro trace is closer to the VCC and VSS top traces than to the VCCand VSS bottom traces.

In Example 8, the subject matter of any one or more of Examples 1-7optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to theland side than to the die side, further including: a capacitor on thedie side; and a semiconductive device on the die side, wherein the microtrace couples the capacitor to the semiconductive device, and whereinthe micro trace is closer to the VCC and VSS bottom traces than to theVCC and VSS top traces.

In Example 9, the subject matter of any one or more of Examples 1-8optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to the dieside than to the land side, further including a capacitor on the dieside.

In Example 10, the subject matter of any one or more of Examples 1-9optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to the dieside than to the land side, further including: a capacitor on the dieside; and a semiconductive device on the die side, wherein the microtrace couples the capacitor to the semiconductive device.

In Example 11, the subject matter of any one or more of Examples 1-10optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to the dieside than to the land side, further including: a capacitor on the dieside; a semiconductive device on the die side, wherein the micro tracecouples the capacitor to the semiconductive device; and a memory-die onthe die side, wherein the memory die is between the semiconductivedevice and the capacitor, and wherein a keep-out zone is between thememory die and the capacitor.

In Example 12, the subject matter of any one or more of Examples 1-11optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to the dieside than to the land side, further including: a capacitor on the dieside; and a semiconductive device on the die side, wherein the microtrace couples the capacitor to the semiconductive device, and whereinthe micro trace is closer to the VCC and VSS top traces than to the VCCand VSS bottom traces.

In Example 13, the subject matter of any one or more of Examples 1-12optionally include wherein the semiconductor package substrate includesa die side and a land side, wherein the micro trace is closer to the dieside than to the land side, further including: a capacitor on the dieside; and a semiconductive device on the die side, wherein the microtrace couples the capacitor to the semiconductive device, and whereinthe micro trace is closer to the VCC and. VSS bottom traces than to theVCC and VSS top traces.

In Example 14, the subject matter of any one or more of Examples 1-13optionally include wherein the semiconductor package substrate includesa die side and a land side, further including: a capacitor on the dieside; a semiconductive device on the die side, wherein the micro tracecouples the capacitor to the semiconductive device; and a keep-out zonebetween the capacitor and the semiconductive device.

In Example 15, the subject matter of any one or more of Examples 1-14optionally include wherein the semiconductor package substrate includesa die side and a land side, further including: a capacitor on the dieside; a first semiconductive device on the die side, wherein the microtrace couples the capacitor to the semiconductive device; a subsequentsemiconductive device on the die side adjacent the first semiconductivedevice; and a keep-out zone between the capacitor and the semiconductivedevice.

In Example 16, the subject matter of any one or more of Examples 1-15optionally include wherein the semiconductor package substrate includesa die side and a land side, further including; a capacitor on the dieside; a semiconductive device on the die side, wherein the micro tracecouples the capacitor to the semiconductive device; a first thermal dieadjacent the semiconductive device, wherein the micro trace is coupledto the first thermal die by a metal-insulator-metal layer; and asubsequent thermal die adjacent the semiconductive device and acrossfrom the first thermal die, wherein the micro trace is coupled to thesubsequent thermal die by a metal-insulator-metal layer.

Example 17 is a process of assembling a semiconductor package substrate,comprising;

configuring a dielectric layer with a micro trace by curing and thinningdielectric material; coupling the micro trace to one of a VCC DC via anda VSS DC via, wherein the VCC DC via and the VSS DC via are adjacent toeach other; forming a VCC DC top trace to the VCC DC via; and forming aVSS DC top trace to the VSS DC via.

In Example 18, the subject matter of Example 17 optionally includeswherein the micro trace is in the semiconductor package substrate,wherein the semiconductor package substrate includes a die side and aland side, further including assembling a capacitor on the die side, andwherein the capacitor is coupled to the micro trace.

In Example 19, the subject matter of any one or more of Examples 17-18optionally include wherein the micro trace is in the semiconductorpackage substrate, wherein the semiconductor package substrate includesa die side and a land side, further including: assembling a capacitor onthe die side, and wherein the capacitor is coupled to the micro trace;and assembling a semiconductive device on the die side, and wherein thecapacitor is coupled to the semiconductive device through the microtrace.

Example 20 is a computing system, comprising: semiconductor packagesubstrate including a die side and a land side; a VCC via in thesemiconductor package substrate, wherein the VCC via is between a VCCtop trace and a VCC bottom trace; a VSS via in the semiconductor packagesubstrate, wherein the VSS via is between a VSS top trace and a VSSbottom trace, wherein the VSS via is adjacent the VCC via; a micro tracethat contacts only one of the VCC via and VSS via, wherein the microtrace is between the VCC and VSS top traces and the VCC and VSS bottomtraces, and wherein the micro trace is thinner than any of the VSS andVCC top traces and the VSS and VCC bottom traces; a mica dielectriclayer contacting micro trace, wherein the micro dielectric layercontacts one of the VCC and VSS top traces, and the VCC and. VSS bottomtraces; a capacitor on the die side, wherein the capacitor is coupled tothe micro trace; a semiconductive device on the die side, wherein thesemiconductive device is coupled to the micro trace; and wherein thesemiconductive device is part of a chipset.

In Example 21, the subject matter of Example 20 optionally includes anelectrical bump array on the land side; and a board that contacts theelectrical bump array, and wherein the board in includes a shell.

The above detailed description includes references to the accompanyingdrawings, which form a part of the detailed description. The drawingsshow, by way of illustration, specific embodiments in which theinvention can be practiced. These embodiments are also referred toherein as “examples.” Such examples can include elements in addition tothose shown or described. However, the present inventors alsocontemplate examples in which only those elements shown or described areprovided. Moreover, the present inventors also contemplate examplesusing any combination or permutation of those elements shown ordescribed (or one or more aspects thereof), either with respect to aparticular example (or one or more aspects thereof), or with respect toother examples (or one or more aspects thereof) shown or describedherein.

In the event of inconsistent usages between this document and anydocuments so incorporated by reference, the usage in this documentcontrols.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one, independent of any otherinstances or usages of “at least one” or “one or more.” In thisdocument, the term “or” is used to refer to a nonexclusive or, such that“A or B” includes “A but not B,” “B but not A,” and “A and B,” unlessotherwise indicated. In this document, the terms “including” and “inwhich” are used as the plain-English equivalents of the respective terms“comprising” and “wherein.” Also, in the following claims, the terms“including” and “comprising” are open-ended, that is, a system, device,article, composition, formulation, or process that includes elements inaddition to those listed after such a term in a claim are still deemedto fall within the scope of that claim. Moreover, in the followingclaims, the terms “first,” “second,” and “third,” etc. are used merelyas labels, and are not intended to impose numerical requirements ontheir objects.

Method examples described herein can be machine or computer-implementedat least in part. Some examples can include a computer-readable mediumor machine-readable medium encoded with instructions operable toconfigure an electrical device to perform methods as described in theabove examples. An implementation of such methods can include code, suchas microcode, assembly language code, a higher-level language code, orthe like. Such code can include computer readable instructions forperforming various methods. The code may form portions of computerprogram products. Further, in an example, the code can be tangiblystored on one or more volatile, non-transitory, or non-volatile tangiblecomputer-readable media, such as during execution or at other times.Examples of these tangible computer-readable media can in include, butare not limited to, hard disks, removable magnetic disks, removableoptical disks (e.g., compact disks and digital video disks), magneticcassettes, memory cards or sticks, random access memories (RAMs), readonly memories (ROMs), and the like.

The above description is intended to be illustrative, and notrestrictive. For example, the above-described examples (or one or moreaspects thereof) may be used in combination with each other. Otherembodiments can be used, such as by one of ordinary skill in the artupon reviewing the above description. The Abstract is provided to complywith 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain thenature of the technical disclosure. It is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims. Also, in the above Detailed Description,various features may be grouped together to streamline the disclosure.This should not be interpreted as intending that an unclaimed disclosedfeature is essential to any claim. Rather, inventive subject matter maylie in less than all features of a particular disclosed embodiment.Thus, the following claims are hereby incorporated into the DetailedDescription as examples or embodiments, with each claim standing on itsown as a separate embodiment, and it is contemplated that suchembodiments can be combined with each other in various combinations orpermutations. The scope of the disclosed embodiments should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

1. A semiconductor package substrate comprising: a VCC via between a VCCtop trace and a VCC bottom trace; a VSS via between a VSS top trace anda VSS bottom trace, wherein the VSS via is adjacent the VCC via; a microtrace that contacts only one of the VCC via and VSS via, wherein themicro trace is between the VCC and VSS top traces and the VCC and VSSbottom traces, and wherein the micro trace is thinner than any of theVSS and VCC top traces and the VSS and VCC bottom traces; and a microdielectric layer contacting the micro trace, wherein the microdielectric layer contacts one of the VCC and VSS top traces and the VCCand VSS bottom traces.
 2. The semiconductor package substrate of claim1, wherein micro trace is closer to the VSS and VCC bottom traces thanto the VSS and VCC top traces.
 3. The semiconductor package substrate ofclaim 1, wherein mien trace is closer to the VSS and VCC top traces thanto the VSS and VCC bottom traces.
 4. The semiconductor package substrateof claim 1, wherein the semiconductor package substrate includes a dieside and a land side, wherein the micro trace is closer to the land sidethan to the die side, further including a capacitor on the die side. 5.The semiconductor package substrate of claim 1, wherein thesemiconductor package substrate includes a die side and a land side,wherein the micro trace is closer to the land side than to the die side,further including: a capacitor on the die side; and a semiconductivedevice on the die side, wherein the micro trace couples the capacitor tothe semiconductive device.
 6. The semiconductor package substrate ofclaim 1, wherein the semiconductor package substrate includes a die sideand a land side, wherein the micro trace is closer to the land side thanto the die side, further including: a capacitor on the die side; asemiconductive device on the die side, wherein the micro trace couplesthe capacitor to the semiconductive device; and a memory-die on the dieside, wherein the memory die is between the semiconductive device andthe capacitor, and wherein a keep-out zone is between the memory die andthe capacitor.
 7. The semiconductor package substrate of claim 1,wherein the semiconductor package substrate includes a die side and aland side, wherein the micro trace is closer to the land side than tothe die side, further including: a capacitor on the die side; and asemiconductive device on the die side, wherein the micro trace couplesthe capacitor to the semiconductive device, and wherein the micro traceis closer to the VCC and VSS top traces than to the VCC and VSS bottomtraces.
 8. The semiconductor package substrate of claim 1, wherein thesemiconductor package substrate includes a die side and a land side,wherein the micro trace is closer to the land side than to the die side,further including: a capacitor on the die side; and a semiconductivedevice on the die side, wherein the micro trace couples the capacitor tothe semiconductive device, and wherein the micro trace is closer to theVCC and VSS bottom traces than to the VCC and VSS top traces.
 9. Thesemiconductor package substrate of claim 1, wherein the semiconductorpackage substrate includes a die side and a land side, wherein the microtrace is closer to the die side than to the land side, further includinga capacitor on the die side.
 10. The semiconductor package substrate ofclaim 1, wherein the semiconductor package substrate includes a die sideand a land side, wherein the micro trace is closer to the die side thanto the land side, further including: a capacitor on the die side; and asemiconductive device on the die side, wherein the micro trace couplesthe capacitor to the semiconductive device.
 11. The semiconductorpackage substrate of claim 1, wherein the semiconductor packagesubstrate includes a die side and a land side, wherein the micro traceis closer to the die side than to the land side, further including: acapacitor on the die side; a semiconductive device on the die side,wherein the micro trace couples the capacitor to the semiconductivedevice; and a memory-die on the die side, wherein the memory die isbetween the semiconductive device and the capacitor, and wherein akeep-out zone is between the memory die and the capacitor.
 12. Thesemiconductor package substrate of claim 1, wherein the semiconductorpackage substrate includes a die side and a land side, wherein the microtrace is closer to the die side than to the land side, furtherincluding: a capacitor on the die side; and a semiconductive device onthe die side, wherein the micro trace couples the capacitor to thesemiconductive device, and wherein the micro trace is closer to the VCCand VSS top traces than to the VCC and VSS bottom traces.
 13. Thesemiconductor package substrate of claim 1, wherein the semiconductorpackage substrate includes a die side and a land side, wherein the microtrace is closer to the die side than to the land side, furtherincluding: a capacitor on the die side; and a semiconductive device onthe die side, wherein the micro trace couples the capacitor to thesemiconductive device, and wherein the micro trace is closer to the VCCand VSS bottom traces than to the VCC and VSS top traces.
 14. Thesemiconductor package substrate of claim 1, wherein the semiconductorpackage substrate includes a die side and a land side, furtherincluding: a capacitor on the die side; a semiconductive device on thedie side, wherein the micro trace couples the capacitor to thesemiconductive device; and a keep-out zone between the capacitor and thesemiconductive device.
 15. The semiconductor package substrate of claim1, wherein the semiconductor package substrate includes a die side and aland side, further including: a capacitor on the die side; a firstsemiconductive device on the die side, wherein the micro trace couplesthe capacitor to the semiconductive device; a subsequent semiconductivedevice on the die side adjacent the first semiconductive device; and akeep-out zone between the capacitor and the semiconductive device. 16.The semiconductor package substrate of claim 1, wherein thesemiconductor package substrate includes a die side and a land side,further including: a capacitor on the die side; a semiconductive deviceon the die side, wherein the micro trace couples the capacitor to thesemiconductive device; a first thermal die adjacent the semiconductivedevice, wherein the micro trace is coupled to the first thermal die by ametal-insulator-metal layer; and a subsequent thermal die adjacent thesemiconductive device and across from the first thermal die, wherein themicro trace is coupled to the subsequent thermal die by ametal-insulator-metal layer.
 17. A process of assembling a semiconductorpackage substrate, comprising; configuring a dielectric layer with amicro trace by curing and thinning dielectric material; coupling themicro trace to one of a VCC DC via and a VSS DC via, wherein the VCC DCvia and the VSS DC via are adjacent to each other; forming a VCC DC toptrace to the VCC DC via; and forming a VSS DC top trace to the VSS DCvia.
 18. The process of claim 17, wherein the micro trace is in thesemiconductor package substrate, wherein the semiconductor packagesubstrate includes a die side and a land side, further includingassembling a capacitor on the die side, and wherein the capacitor iscoupled to the micro trace.
 19. The process of claim 17, wherein themicro trace is in the semiconductor package substrate, wherein thesemiconductor package substrate includes a die side and a land side,further including: assembling a capacitor on the die side, and whereinthe capacitor is coupled to the micro trace; and assembling asemiconductive device on the die side, and wherein the capacitor iscoupled to the semiconductive device through the micro trace.
 20. Acomputing system, comprising: semiconductor package substrate includinga die side and a land side; a VCC via in the semiconductor packagesubstrate, wherein the VCC via is between a VCC top trace and a VCCbottom trace; a VSS via in the semiconductor package substrate, whereinthe VSS via is between a VSS top trace and a VSS bottom trace, whereinthe VSS via is adjacent the VCC via; a micro trace that contacts onlyone of the VCC via and VSS via, wherein the micro trace is between theVCC and VSS top traces and the VCC and VSS bottom traces, and whereinthe micro trace is thinner than any of the VSS and VCC top traces andthe VSS and VCC bottom traces; a mica dielectric layer contacting themicro trace, wherein the micro dielectric layer contacts one of the VCCand VSS top traces, and the VCC and VSS bottom traces; a capacitor onthe die side, wherein the capacitor is coupled to the micro trace; asemiconductive device on the die side, wherein the semiconductive deviceis coupled to the micro trace; and wherein the semiconductive device ispart of a chipset.
 21. The computing system of claim 20, furtherincluding: an electrical bump array on the land side; and a board thatcontacts the electrical bump array, and wherein the board includes ashell.